The invention relates to technology for designing and verifying an integrated circuit (“IC”) or electronic circuit design.
A semiconductor integrated circuit (IC) or an electronic circuit has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an electronic circuit, a designer first creates high level behavior descriptions of the electronic circuit device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the electronic circuit device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information on circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An electronic circuit designer may use a set of EDA application programs to create a physical electronic circuit design layout from a logical circuit design. The EDA application uses geometric shapes of different materials to create the designs of the various electrical components in an electronic circuit and to represent electronic circuit components as geometric objects with varying shapes and sizes. Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic component design and/or circuit design blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. In a typical electronic circuit design flow, routing involves assigning wires and vias to create a circuit connection.
In the Integrated Circuit (IC) design, electronic components and wiring are represented by a set of geometric shapes and patterns from a physical perspective. Electronic design automation (EDA) tools interact with these shapes and patterns throughout the IC design and verification process. The electronic circuit design then goes through various stages of verification and optimization via a set of EDA Aesting and analysis tools. Verification may include, for example, design rule checking (DRC) to verify whether or not various electronic circuit parameters comply with various design rules that are established for the respective electronic circuit parameters. For example, the patterns and shapes in the design are routinely checked with the Design Rules—Design Rules Checking (DRC). Design rules are a series of parameters provided by semiconductor manufacturers, specifying geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes.
DRC enables a designer to verify the correctness of his or her design and to achieve a high overall yield and reliability for the design. In other words, a routing solution, for example, is usually driven by various design rules against which the electronic design may be checked and a set of requirements such as spacing requirements between two or more objects and routing object size requirements. The routing applications such as a router then ensure that these design rules and various sets of requirements are met in order to have a working electronic circuit. For example, DRC governs how an object has to be spaced relative to another object and to meet the width requirement. That is, after the physical mask layout is generated for an electronic circuit, the layout is measured by a set of constraints, rules, or requirements, such as geometric constraints or rules for the particular processes the electronic circuit is designed to perform, to ensure high yield and reliability by verifying that the electronic design meets the process constraints.
An electronic circuit often comprises a plurality of blocks or modules which are highly state-dependent because the actions of the plurality of blocks or modules depend not only on their inputs but also on what events have previously happened. The electronic circuit components, or, more precisely, the geometries in the electronic circuit design in a verification flow, such as a design rule checking process, are usually grouped into layers. Depending upon the type of verification operations, typical examples of such layers comprise drawn layers which represent the original layout data, polygon layers each of which constitutes the output of a layer creation operation such as a Boolean operation, an area function, or a polygon operation. Typical examples of such layers may also comprise edge layers, each of which represents one or more edges of merged polygons as outputted by operations such as some measurement operations. Another exemplary layer is an error layer which comprises a set of one or more edges from a measurement operation.
Such a hierarchical design for an electronic circuit defines the underlying circuit as a plurality of smaller modules, blocks, cells, or cellviews, each of which may be further broken down to comprise another set of even smaller sub-modules or sub-blocks and eventually down to individual circuit elements or components such as individual pieces of interconnects. This hierarchical nature of the electronic design allows the circuit designers not only to consider the entire electronic circuit in a modular way but also to consider each of the modules, blocks, sub-modules, sub-blocks, or the individual circuit elements individually, if desired. In addition, this hierarchical design allows for scoping for variable declaration, procedure calls, and/or policy determination for each of the various levels in the hierarchy.
Conventional approaches for verification of electronic circuits such as language-based DRC or image-based DRC operate upon a flat design. It is noted that a flat design may be considered as an electronic design with one cell in the sense that every circuit element in the electronic design belongs to the single cell. With these conventional approaches, a cell-based hierarchical input for an electronic design is flattened, and the entire design is internally represented as one large cell. The language-based DRC (such as a rule-based DRC or a model-based DRC) or an image-based DRC is then performed against this flattened design.
Compared to flat designs, hierarchical designs offer various advantages such as containing a potential state or transition explosion problem when composing sub-states, capability and relative ease in modeling complex hierarchical control flow with transitions spanning different levels of the behaviors of the electronic circuit, and the capability of multi-thread computation, all of which are known, typical problems of a flat design. In addition, a flat design has been well known to be ill suited for parallelization and multi-threaded computation.
On the other hand, the complex interactions between multiple elements which may even belong to multiple layers in the hierarchy of the electronic design have imposed an almost insurmountable barrier to performing verification of hierarchical electronic circuit designs because analyzing such a hierarchical design is known to be NPC (nondeterministic polynomial time-complete) in the size of the hierarchical design. This barrier is further exacerbated by the choice of hierarchy in a given electronic circuit design because circuit designers often determines the hierarchies based on factors or reason completely unrelated to verification. For example, a circuit designer may determine the hierarchies of an electronic circuit design based on the ease of logical understanding of the circuit functions.
In addition, insertion of metal fills or dummy fills (hereinafter, the fill structures) is a technique that is commonly used to enhance integrity and assure planarity of the deposited layers on an electronic circuit. Without the support of the fill structures, undesired topological variations, such as variation in thickness uniformity, copper dishing or erosion due to one or more patterns in the vicinity in a CMP (chemical mechanical polishing) process, etc. may occur. These variations may negatively affect the electronic circuit in terms of yield, performance, etc.
For example, without the support of the fill structures, layers may sag and thus allow conductors of different layers to get too close in violation of a spacing design rule. The fill structures may also affect the electrical operations or characteristics of the underlying circuit, in particular the capacitance between connecting conductors. The fill structures are thus inserted into the electronic design to address these issues and typically include many pieces.
The insertion of the fill structures often involves one or even multiple layers in the electronic circuit. Recent approaches for inserting the fill structures call for the insertion of appropriate fill structures on one layer to resolve potential variations that are caused by that very layer or are propagated from another layer(s). For example, a given layer in an electronic design may not be allowed to accommodate any fill structures or may not have sufficient area to accommodate enough fill structures to successfully resolve the variations. A typical approach is not to add the fill structures or sufficient fill structures into that given layer and allows the variations to propagate to the second layer(s). The typical approach then adds appropriate fill structures to the second layer(s) to address the variations on the second layer(s) as well as the variations propagated from the given layer to the second layer(s). In dealing with such tasks as inserting fill structures in multiple layers, conventional approaches generally require flattening the electronic design despite the electronic circuit design started as a hierarchical design.
Nonetheless, conventional approaches invariably utilize the geometries in the cell(s) or cellview(s) to process the Boolean operations, which are often included in, for example, the insertion of metal or dummy fill or in the language-based or image-based design rule checking, and generate the output of the Boolean operations in a flat structure and are incapable of generating the output of the Boolean operations in a hierarchical structure.
Therefore, there exists a need for a method, a system, and an article of manufacture for creating a hierarchical output for a Boolean operation which is operated upon an electronic design.